
-- VHDL Instantiation Created from source file Read_UART_RAM.vhd -- 11:24:05 03/21/2012
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT Read_UART_RAM
	PORT(
		Data_in : IN std_logic_vector(7 downto 0);
		Reset : IN std_logic;
		Klok : IN std_logic;
		Buffer_full : IN std_logic;
		Data_present : IN std_logic;          
		read_buffer : OUT std_logic;
		Write_RAM : OUT std_logic;
		Done : OUT std_logic;
		Adres_RAM : OUT std_logic_vector(3 downto 0);
		Data_RAM : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	Inst_Read_UART_RAM: Read_UART_RAM PORT MAP(
		Data_in => ,
		Reset => ,
		Klok => ,
		Buffer_full => ,
		Data_present => ,
		read_buffer => ,
		Write_RAM => ,
		Done => ,
		Adres_RAM => ,
		Data_RAM => 
	);


